Digital System Test And Testable Design: Using ... Link

The book describes on-chip decompression algorithms in Verilog, providing a realistic look at how these impact overall chip area and performance. Key Technical Coverage

Logic BIST basics, test pattern generation, and output response analysis. Digital System Test and Testable Design: Using ...

Random and deterministic test generation methods, plus sequential circuit test generation. test pattern generation

The material is structured into two main parts: developing test environments and implementing testable hardware. Key Topics Covered Digital System Test and Testable Design: Using ...

Gate-level faults, fault collapsing, and structural modeling in Verilog.

The text treats testing and testability as integral parts of the digital design process rather than afterthoughts.

This book is widely used as a primary text in and Design for Testability courses. More information can be found at Springer Nature or through retailers like Amazon .